Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering Technical Report: UT-CERC-TR-NAT02-1
نویسندگان
چکیده
This paper describes a technique for minimizing power dissipation that is also capable of reducing the area overhead of the circuit, compared to a random ordering of the scan cells. For a given set of test-vectors, we find the (locally) optimal re-ordering of the scan cells that minimizes a score function, which is a linear combination of the power and the area overhead. The score function has a trade-off parameter λ that can be used by the designer to specify the relative importance of area overhead minimization and power minimization. Our proposed greedy algorithm finds the best ordering for a given value of λ. The strength of our algorithm lies in the fact that we use a novel dynamic minimum transition fill (MT-fill) technique for the unspecified bits in the test vector. Experiments performed on the ISCAS-89 benchmark suite show a reduction in power (e.g., 70% for circuit s13207, λ = 500) as well as a reduction in layout area (e.g., 6.72% for circuit s13207, λ = 500).
منابع مشابه
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random ordering of the scan cells. For a given test set, our proposed greedy algorithm finds the (locally) optimal scan cell ordering for a given value of λ, which is a trade-off parameter that can be used by the designer to...
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